Computer Organization & Architecture (3140707) MCQs

MCQs of Basic Computer Organization and Design

Showing 31 to 40 out of 50 Questions
1 2 3 4 5
31.
Which operation decoder signal is set to perform BUN instruction?
(a) D4
(b) D2
(c) D0
(d) D5
Answer:

Option (a)

32.
Operation decoder signal D1 is set to execute which instruction?
(a) AND
(b) LDA
(c) ADD
(d) STA
Answer:

Option (c)

33.
Which of the following MRI instruction is executed in only one timing cycle after fetch & decode?
(a) LDA
(b) STA
(c) AND
(d) ADD
Answer:

Option (b)

34.
Which register is used to perform arithmetic & logical operation with data stored in AC?
(a) AR
(b) AC
(c) IR
(d) DR
Answer:

Option (d)

35.
Which instruction performs the function usually referred to as a subroutine call?
(a) STA
(b) BNA
(c) BSA
(d) BUN
Answer:

Option (c)

36.
Which mode of BUN instruction is used at end of the subroutine to perform return function?
(a) Direct
(b) Indirect
(c) Both can be used
(d) Wrong statement
Answer:

Option (b)

37.
Which instruction needs maximum (7) timing signals to execute?
(a) ISZ
(b) BUN
(c) BSA
(d) LDA
Answer:

Option (a)

38.
INPR & OUTR registers communicate with a communication interface in _______ and with AC in _______.
(a) Parallel, Serial
(b) Serial, Serial
(c) Serial, Parallel
(d) Parallel, Parallel
Answer:

Option (c)

39.
Initially, the input flag FGI is?
(a) X (Don’t care)
(b) Depends on input device
(c) 1
(d) 0
Answer:

Option (d)

40.
Initially, the output flag FGO is?
(a) X (Don’t care)
(b) Depends on output device
(c) 1
(d) 0
Answer:

Option (c)

Showing 31 to 40 out of 50 Questions
1 2 3 4 5